This is an official U.S. Navy Web site
The Configurable Fault Tolerant Processor experiment aims to develop a flexible and reprogrammable system on a chip that is also immune to radiation effects in the harsh space environment. The basic architecture of the CFTP is a Triple Modular Redundant microprocessor instantiated on a Field Programmable Gate Array. The configurable processor provides the flexibility needed to support dynamic mission requirements, allowing on-orbit upgrades, reconfigurations, and modifications to the architecture, while the Triple Modular Redundancy provides an additional level of protection from the radiation environment.
This website is intended as a resource for those working on the CFTP. If there is additional information you feel would be beneficial to the team, contact the webmaster at the address below with comments or suggestions.